37#if !defined(_SPANDSP_V80_H_)
38#define _SPANDSP_V80_H_
45 V80_FROM_DTE_MFGEXTEND = 0x20,
46 V80_FROM_DTE_MFG1 = 0x21,
47 V80_FROM_DTE_MFG2 = 0x22,
48 V80_FROM_DTE_MFG3 = 0x23,
49 V80_FROM_DTE_MFG4 = 0x24,
50 V80_FROM_DTE_MFG5 = 0x25,
51 V80_FROM_DTE_MFG6 = 0x26,
52 V80_FROM_DTE_MFG7 = 0x27,
53 V80_FROM_DTE_MFG8 = 0x28,
54 V80_FROM_DTE_MFG9 = 0x29,
55 V80_FROM_DTE_MFG10 = 0x2A,
56 V80_FROM_DTE_MFG11 = 0x2B,
57 V80_FROM_DTE_MFG12 = 0x2C,
58 V80_FROM_DTE_MFG13 = 0x2D,
59 V80_FROM_DTE_MFG14 = 0x2E,
60 V80_FROM_DTE_MFG15 = 0x2F,
61 V80_FROM_DTE_EXTEND0 = 0x40,
62 V80_FROM_DTE_EXTEND1 = 0x41,
63 V80_FROM_DTE_CIRCUIT_105_OFF = 0x42,
64 V80_FROM_DTE_CIRCUIT_105_ON = 0x43,
65 V80_FROM_DTE_CIRCUIT_108_OFF = 0x44,
66 V80_FROM_DTE_CIRCUIT_108_ON = 0x45,
67 V80_FROM_DTE_CIRCUIT_133_OFF = 0x46,
68 V80_FROM_DTE_CIRCUIT_133_ON = 0x47,
69 V80_FROM_DTE_SINGLE_EM_P = 0x58,
70 V80_FROM_DTE_DOUBLE_EM_P = 0x59,
71 V80_FROM_DTE_FLOW_OFF = 0x5A,
72 V80_FROM_DTE_FLOW_ON = 0x5B,
73 V80_FROM_DTE_SINGLE_EM = 0x5C,
74 V80_FROM_DTE_DOUBLE_EM = 0x5D,
75 V80_FROM_DTE_POLL = 0x5E,
78 V80_FROM_DCE_EXTENDMFG = 0x30,
79 V80_FROM_DCE_MFG1 = 0x31,
80 V80_FROM_DCE_MFG2 = 0x32,
81 V80_FROM_DCE_MFG3 = 0x33,
82 V80_FROM_DCE_MFG4 = 0x34,
83 V80_FROM_DCE_MFG5 = 0x35,
84 V80_FROM_DCE_MFG6 = 0x36,
85 V80_FROM_DCE_MFG7 = 0x37,
86 V80_FROM_DCE_MFG8 = 0x38,
87 V80_FROM_DCE_MFG9 = 0x39,
88 V80_FROM_DCE_MFG10 = 0x3A,
89 V80_FROM_DCE_MFG11 = 0x3B,
90 V80_FROM_DCE_MFG12 = 0x3C,
91 V80_FROM_DCE_MFG13 = 0x3D,
92 V80_FROM_DCE_MFG14 = 0x3E,
93 V80_FROM_DCE_MFG15 = 0x3F,
94 V80_FROM_DCE_EXTEND0 = 0x60,
95 V80_FROM_DCE_EXTEND1 = 0x61,
96 V80_FROM_DCE_CIRCUIT_106_OFF = 0x62,
97 V80_FROM_DCE_CIRCUIT_106_ON = 0x63,
98 V80_FROM_DCE_CIRCUIT_107_OFF = 0x64,
99 V80_FROM_DCE_CIRCUIT_107_ON = 0x65,
100 V80_FROM_DCE_CIRCUIT_109_OFF = 0x66,
101 V80_FROM_DCE_CIRCUIT_109_ON = 0x67,
102 V80_FROM_DCE_CIRCUIT_110_OFF = 0x68,
103 V80_FROM_DCE_CIRCUIT_110_ON = 0x69,
104 V80_FROM_DCE_CIRCUIT_125_OFF = 0x6A,
105 V80_FROM_DCE_CIRCUIT_125_ON = 0x6B,
106 V80_FROM_DCE_CIRCUIT_132_OFF = 0x6C,
107 V80_FROM_DCE_CIRCUIT_132_ON = 0x6D,
108 V80_FROM_DCE_CIRCUIT_142_OFF = 0x6E,
109 V80_FROM_DCE_CIRCUIT_142_ON = 0x6F,
110 V80_FROM_DCE_SINGLE_EM_P = 0x76,
111 V80_FROM_DCE_DOUBLE_EM_P = 0x77,
112 V80_FROM_DCE_OFF_LINE = 0x78,
113 V80_FROM_DCE_ON_LINE = 0x79,
114 V80_FROM_DCE_FLOW_OFF = 0x7A,
115 V80_FROM_DCE_FLOW_ON = 0x7B,
116 V80_FROM_DCE_SINGLE_EM = 0x7C,
117 V80_FROM_DCE_DOUBLE_EM = 0x7D,
118 V80_FROM_DCE_POLL = 0x7E,
121 V80_TRANSPARENCY_T1 = 0x5C,
122 V80_TRANSPARENCY_T5 = 0x5D,
123 V80_TRANSPARENCY_T2 = 0x76,
124 V80_TRANSPARENCY_T6 = 0x77,
125 V80_TRANSPARENCY_T3 = 0xA0,
126 V80_TRANSPARENCY_T4 = 0xA1,
127 V80_TRANSPARENCY_T7 = 0xA2,
128 V80_TRANSPARENCY_T8 = 0xA3,
129 V80_TRANSPARENCY_T9 = 0xA4,
130 V80_TRANSPARENCY_T10 = 0xA5,
131 V80_TRANSPARENCY_T11 = 0xA6,
132 V80_TRANSPARENCY_T12 = 0xA7,
133 V80_TRANSPARENCY_T13 = 0xA8,
134 V80_TRANSPARENCY_T14 = 0xA9,
135 V80_TRANSPARENCY_T15 = 0xAA,
136 V80_TRANSPARENCY_T16 = 0xAB,
137 V80_TRANSPARENCY_T17 = 0xAC,
138 V80_TRANSPARENCY_T18 = 0xAD,
139 V80_TRANSPARENCY_T19 = 0xAE,
140 V80_TRANSPARENCY_T20 = 0xAF,
171 V80_BIT_RATE_1200 = 0x20,
172 V80_BIT_RATE_2400 = 0x21,
173 V80_BIT_RATE_4800 = 0x22,
174 V80_BIT_RATE_7200 = 0x23,
175 V80_BIT_RATE_9600 = 0x24,
176 V80_BIT_RATE_12000 = 0x25,
177 V80_BIT_RATE_16800 = 0x27,
178 V80_BIT_RATE_19200 = 0x28,
179 V80_BIT_RATE_21600 = 0x29,
180 V80_BIT_RATE_24000 = 0x2A,
181 V80_BIT_RATE_26400 = 0x2B,
182 V80_BIT_RATE_28800 = 0x2C,
183 V80_BIT_RATE_31200 = 0x2D,
184 V80_BIT_RATE_33600 = 0x2E,
185 V80_BIT_RATE_32000 = 0x2F,
186 V80_BIT_RATE_56000 = 0x30,
187 V80_BIT_RATE_64000 = 0x31
192#if defined(__cplusplus)
197SPAN_DECLARE(
const char *) v80_escape_to_str(
int esc);
199SPAN_DECLARE(
int) v80_bit_rate_code_to_bit_rate(
int rate_code);
201#if defined(__cplusplus)
Definition private/v80.h:30